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march 2013 docid9986 rev 2 1/22 AN1753 application note software uart using st7lite0 12-bit autoreload timer introduction this application note describes a software implementation of a universal asynchronous receiver/transmitter (uart). this can be used on devices with no on-chip sci peripheral. in this example, a software uart is implemented for the st7lite0, using the 12-bit autoreload timer and two i/o ports for asynchronous receive and transmit. the uart software provides the following features: ? half-duplex operation ? asynchronous operation ? flexible data formats (7 or 8 data bits, 1 or 2 stop bits) ? baud rate: 2400 to 19200 baud to test this interrup t-driven software uart, you can use the ?hyperterminal? application running on a windows pc. the program code is quite small (357 bytes) and can easily be adapted to specific application requirements. table 1 lists the microcontrollers and software concerned by this application note. table 1. applicable products and software type part numbers or product categories microcontrollers st7lite02y0 , st7lite05y0, st7lite09y0 software stsw-st7094 www.st.com
contents AN1753 2/22 docid9986 rev 2 contents 1 uart communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 rs232 communication with a pc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 st7flite0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 input initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 auto-reload timer register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 uart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 baud rate definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 majority-voting system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 status handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 transmit and receive implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 functional software flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 main software routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 software flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 test procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid9986 rev 2 3/22 AN1753 list of figures list of figures figure 1. st7 uart communication set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. majority-voting system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. main flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. output compare interrup t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. transmit routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. receive data routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. output compare transmit flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. output compare receive flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. ei1 interr upt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
uart communication AN1753 4/22 docid9986 rev 2 1 uart communication the main features of a standard uart are summarized below. 1.1 main features the uart offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the uart allows a very wide range of baud rates and different baud rates for transmission and reception. in uart communication, a minimum of onl y two signals are needed, one for transmission and one for reception. no clock signal is needed as it works in asynchronous mode. each device has to have a transmit data output pin (the pa3 pin is used in our example for the st7flite0) and a receive data input pin (pa7 pin in our example). (refer to figure 1 .) figure 1. st7 uart communication set-up you must be very careful to identify the use of each pin. a simple method is to put the device in transmission and check with an oscilloscope if a transmissi on frame is present or not. 1.2 baud rate transmission and reception can be driven by their own baud rate generator. however, be aware that, for a correct communication, the receiver must have a reception baud rate strictly equal to the transmis sion baud rate of the transmitte r. if not, the communication will be corrupted. as long as this condition is met, a wide range of baud rates is possible. 1.3 frame any transmission is least signif icant bit first. a data word is usually 8 bits long. a data frame begins with a ?start bit?, which is a ?0? bit and ends with a stop bit, which is a ?1? bit (see figure 2 ). st7 system rdi tdo terminal device (tdo) pa3 (rdi) pa7 st7flite0 (host)
docid9986 rev 2 5/22 AN1753 uart communication figure 2. frames in some cases, a 9th bit can be used, as a parity bit or as a second stop bit. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit 8-bit word length data frame next data frame
rs232 communication with a pc AN1753 6/22 docid9986 rev 2 2 rs232 communication with a pc 2.1 main features electrical and protocol characteristics of rs232 are different from those used by the uart. in rs232 communication, high level is typically +7v and low level is typically -7v, while the st7lite0 i/os work at cmos levels (0, +5v). furthermore, the polarities are different. a ?1 ? bit coming from the uart corresponds to a ?0? bit in rs232, and a ?0? bit to a ?1? bit. it is tr ue for all bits including the start and stop bits. so it is necessary to implement a conversion between the pc and the st7lite0. in the application, a max232 is used for this purpose. 2.2 pc configuration the pc will be used as a terminal interface. ?hyperterminal?, the terminal application software, is used as an interfacing software to test the func tion [.zip file attached]. the test environment is windows. under windows, open the hyperterminal applicatio n. to configure it, go to the port settings and set the parameters to your application requirements. the options in this window must be the same as the ones defined for your st7flite0 communication device, except the port. after selecting the right serial communication port, select the same baud rate as the one set for the st7lite0. as the pc accepts only one baud rate, transmission and reception baud rates will have the same value. data word can be 8/7 bits , but you can choose to use 1 or 2 stop bits. ?flow control? can be either xon/xoff or none. the pc is then correctly configured.
docid9986 rev 2 7/22 AN1753 st7flite0 configuration 3 st7flite0 configuration 3.1 clock source this application is implemented using an st7flite0 device with an 8 mhz internal clock. pll * 8 is used to generate this 8 mhz clock. 3.2 input initialization two pins of the st7flite0 are used: ? pa3: pin of porta ? pa7: pin of porta with interrupt pin pa3 is a normal input/output port pin with no alternate function, used for transmission. during the initialization, it is configured as an output. pin pa7 is a normal input/output port pin with no alternate function, used for data receive. during the initialization, it is configured as an input. while in receive mode, at start, the same pin is used with interrupt enabled (?ei1?) to sense the start bit. so this pin is configured with ?pull up interr upt input? by setting paddr to 0 & paor to 1. to set the interrupt sensitivity ?falling edge only?, you have to set is11=1 & is10=0 in the eicr register. refer to the device datasheet for a detailed de scription of the i/o and interrupt control registers. 3.3 auto-reload timer register configuration the at timer is based on a free running 12-bit upcounter with 12-bit auto reload register (atr). apart from this, it also includes other functions such as pwm signal generator, output compare function, etc. the ?output compare? function is used for this application. to use it, the oe bit must be 0, otherwise the compare is done with the shadow register instead of the dcrx register. the software must then write a 12-b it value in the dcr0h and dcr0l registers. when the 12-bit upcounter (cntr) reaches the value stored in the dcr0h and dcr0l registers, the cmpf0 bit in the pwm0csr register is set and an interrupt request is generated, provided that the cmpie bit is set. the registers that are used in the application note are: timer control status register (atcsr): ? ck1, ck0: select the clock frequency of the counter. ? for fcounter = fcpu, set ck1=1 and ck0=0 ? cmpie: allows to mask the interrup t generation when the cmpf bit is set: ? 0: the cmpf interrupt is disabled ? 1: the cmpf inte rrupt is enabled cmpie ovfie ovf ck0 ck1 0 0 0
st7flite0 configuration AN1753 8/22 docid9986 rev 2 pwm0 control/status register (pwm0csr): ? cmpf0: indicates that the upcounter va lue matches the dcr register value: ? 0: the upcounter value does not match the dcr value. ? 1: the upcounter value matches the dcr value. pwm output control register (pwmcr): ? oe0: when set to 1, the pwm0 output is enabled timer initialization write to dcrx registers with the required value. the output compare function must be enabled. to do this, reset the oe bit in the pwmcr register: this will disable the pwm output. to configure fcounter = fcpu, set ck1=1 and ck0=0 an to enable the cmpf interrupt, set cmpie=1 in the atcsr register. cmpf0 0 0 0 0 0 0 op0 0 0 0 oe0 0 0 0 0
docid9986 rev 2 9/22 AN1753 uart implementation 4 uart implementation 4.1 baud rate definition the autoreload timer is used to generate the baud rate. the autoreload timer clock (fcounter) is the same as the fcpu cl ock, which is an 8 mhz internal clock. the example below describes how this baud is generated: - baudrate = 2400 - fcpu = 8mhz (so clock period is 125 ns) - in the application fcounter = fcpu so to get 2400 baud the ?prescaler? required is, prescaler = fcpu / baud prescaler = 8 * 10 6 / 2400 = 0.0033333333 * 10 6 = 3333.33 decimal = d05 hex (= 1 bit delay count) so in software dcrx will be dcr0h = 0d + cntrh dcr0l = 05 + cntrl to generate one bit delay when 2400 baud is required for half bit period ?prescaler? is, prescaler = one bit / 2 = 1666.66 (decimal) = 682 hex (= 1/2 bit delay) dcr0h = 06 + cntrh dcr0l = 82 + cntrl the software provided with this application not e has been functionally tested in the range 2400 to 19200 baud. 4.2 majority-voting system compared to the transmit section, the receiv e section is complex. thus, to avoid possible errors in detecting the exact bit status beca use of line noise, etc., this program uses a majority-voting system. when the st7lite0 is in receive mode, it reads (samples) each bit three times in the middle of th e bit time. to determine its exact state, it compares the number of 1?s with the number of 0?s. if there are more ?1?s than ?0?s, the bit received is a ?1?, else it is a ?0?. (see figure 3 ) figure 3. majority-voting system this section is only used for the receive part. you can change it to suit your requirements. 012 3 4 5 67 1st sample 2nd sample 3rd sample start stop
uart implementation AN1753 10/22 docid9986 rev 2 4.3 status handling to keep track of the status during a program execution, the software uses the ?sci_status? variable. bits 0-4 of this variable are used to hold the system status. definition of each flag: sp: reception mode sampling phase br: byte received flag re: reception enable bs: byte sent flag te: transmission enable 4.4 transmit and receive implementation the transmission mode gets executed after power on. to transmit data, the program uses port pin pa3 in output mode with the ?output compare? interrupt. on e bit is transmitted during each interrupt, generated after a bit delay when the 12-bit upcounter (cntr) reaches the value (=1 bit delay) stored in the dcr0h and dcr0l registers. for a duty cycle register (dcr0l/dcr0h), the value depend s on the required baud rate and clock frequency. for receive mode, the program uses port pin pa7 in input mode along with its interrupt and output compare functions. to sense the start bit, the ?ei1? interrupt is used and configured as ?falling edge only?. in this inte rrupt routine, the program sets the atr - the output compare value for a half bit delay (a) - and disables the ?ei1? interrupt to use pa7 in normal input mode, in order to receive the entire frame. this half bit delay is used to sample a bit in the middle of it. after receiving a start bit in an output compare interrupt, the same interrupt routine gets executed each time a bit must be received. to receive each bit correctly, the majority-voting system is implem ented in this interrupt routine. the interrupt strategy used in the software to transmit and receive allows other applications to work at the same time. note: error handling : this program does not handle communication errors (e.g. frame errors). no handshaking is implemented. for better performance at high baud rates, it is recommended to use character transmission rather than string transmission. sp br re bs te a. the user can adjust this value depending on the baud rate.
docid9986 rev 2 11/22 AN1753 hardware setup 5 hardware setup a general system configuration is shown in figure 1 . the st7flite0 is connected to an rs-232 line driver chip which is in turn connected to any rs-232-compatible device. the rs-232 line driver is needed to convert the 5-vo lt logic level of the st7flite0 to the proper rs-232 line voltages, and vice versa. figure 4 shows a specific example of a hardware setup required for uart in which the st7flite0 processor and rs-232 driver/ receiver are used. you can use different driver/receiver in your application. for exampl e, you can use an mc14c88/ 89 as a low cost solution. the receive data pin (rd) of the pc serial port must correspond to the pa3 pin of the st7flite0, and the transmit data pin (td) to the pa7 pin. caution: the three main devices (pc, st 7lite0, max232) must have the same electrical reference (gnd). for a detailed description of max232, please refer to the datasheet. figure 4. test setup pc terminal serial port td rd ground max232 in out out in st7flite0 gnd gnd gnd pa7 pin pa3 pin
functional software flow AN1753 12/22 docid9986 rev 2 6 functional software flow the character format used is ?ascii?. before starting a communication, you should configure the communication parameters to your requirements. you can select the baud rate, number of bits and stop bits in different combinations. however, for a correct communication, the receiver must have a reception baud rate strictly equal to the transmission baud rate of the transmitter. if no t, the communication will be corrupted. so you have to configure the ?hyperterminal? correctly. to configure the device, you must set del_1 bh, del_1bl, del_sampl, del_samph, stop_bit and txrx_data_lnth correctly in your software. after power on, the st7flite0 goes to transmit mode. it initiates the communication by transmitting character ?$ ? in ascii format and then goes to receive mode. the pc then receives this character on its serial port, wh ich can be viewed in the hyperterminal window. you then have to press a key (character) to tr ansmit. after pressing a character key, it gets transmitted and the st7lite0 receives it. the st7lite0 then sends the same received character to the pc. this sequence c an be repeated continuously (see figure 5 ). 6.1 main software routines the uart software consists of 4 main routines: ? tx_data ? rx_data ? ei1_interrupt ? opcomp_int tx_data: this routine is used to transmit data in bi t format stored in variable ?tx_byte?. it also takes care of the synchronization and of the output compare interrupt. the at timer is initialized to the application co nfiguration inside this routine. rx_data: this routine is used to receive data on the input pin in bit format and stores it in ?rx_byte?. to detect a start bit, it in itializes the pa7 pin in interrupt mode. ei1_interrupt: this ?ei1? interrupt routine gets executed only once during receive data when pa7 receives a start (high to low edge) bit. it also initiates the at timer for a half bit duration. opcomp_int: this routine gets executed in both transmit and receive modes. during a tx_dataroutine execution, it gets executed for each data bit transfer. it is actually used to transmit data on the txd (pa3) pin along with the start and stop bits. in receive mode, it gets executed for each data bit received, including the start and stop bits. the majority-voting system is implemented in the same section of code.
docid9986 rev 2 13/22 AN1753 functional software flow 6.2 software flow charts the flowcharts below represent the application program flow. figure 5. main flowchart figure 6. output compare interrupt t rx_data tx_data tx_byte = rx_byte main initialize port & variables initiate transmission is it 1st bit? no yes init dcrx with cntrx transmit/receive go on ?transmit routine? go on ?receive routine? opcomp_int
functional software flow AN1753 14/22 docid9986 rev 2 figure 7. transmit routine set ?te? flag ret ?bs? flag set ? tx_data set clock & enable out- set synchronization delay rim sim put compare interrupt no yes
docid9986 rev 2 15/22 AN1753 functional software flow figure 8. receive data routine rx_data set ?re? flag init required variable put ?rxd? in input inter- rupt mode. set eicr reg. ret ?br? flag set ? no yes rim sim
functional software flow AN1753 16/22 docid9986 rev 2 figure 9. output compare transmit flow transmit routine send ?start? bit yes no a bit_count= ?0? set ?bs? flag in ?sci_status? var. disable interrupt & stop timer clock b send ?stop?bit a all ?data? sent? no yes yes no transmit ?data? bit load ?cntr? with 1 bit delay count clear prev. interrupt & set compare interrupt iret b ? ?frame? sent?
docid9986 rev 2 17/22 AN1753 functional software flow figure 10. output compare receive flow receive routine yes no b full?frame? a set ?br? flag disable interrupt & stop timer clock received? read ?rxd? & apply majority voting system ?start? yes no no need yes ? read & check for ?stop?? need read & check for store received data c c a ?start? bit condition ?stop? bit condition
functional software flow AN1753 18/22 docid9986 rev 2 figure 11. ei1 interrupt routine iret read cntrx set dcrx for 0.5 bit set ?sp? flag & put ?rxd? in normal input mode clear pending interrupt enable output compare interrupt & select clock ei1_int delay
docid9986 rev 2 19/22 AN1753 test procedure 7 test procedure 1. connect both the communication and terminal equipment as shown in figure 4 . 2. open and configure the ?hyperterminal ?application [port, baud rate, etc.]. 3. power on the st7lite0. 4. on the terminal, you should get ?$? as a starting character (if not, then check the link between the terminal and the st7lite0 and check the communication settings). 5. press a key to send a character. 6. the same character should be returned by the st7lite0 (check the ?hyperterminal? window). 7. continue by repeating the two previous steps.
software AN1753 20/22 docid9986 rev 2 8 software the complete software can be found on the st in ternet website in a zip ped file format. it is intended for use as an example only. it is up to you to adapt it to your specific application. the source file is for guidance only. stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with re spect to any claims arising from use of this software.
docid9986 rev 2 21/22 AN1753 revision history 9 revision history table 2. document revision history date revision changes 07-nov-2003 1 initial release. 29-mar-2013 2 revalidation replaced ?st7? by ?st7lite0? in the title and the introduction , and added table 1: applicable products and tools .
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